View WM8736_51812.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

WM8736 24-bit, 96kHz 6-Channel DAC with Volume Control
Production Data, January 2001, Rev 2.1
DESCRIPTION
The WM8736 is a high performance 6-channel DAC designed for audio applications such as DVD, home theatre systems, and digital TV. The WM8736 supports data input word lengths from 16 to 24-bits and sampling rates up to 96kHz. The WM8736 consists of a serial interface port, digital interpolation filters, multi-bit sigma delta modulators and 6 DACs in a small 28-pin SSOP package. The WM8736 also includes a digitally controllable mute and attenuator function on each channel. The WM8736 supports a variety of connection schemes for audio DAC control. The SPI-compatible serial port provides access to a wide range of features including on-chip mute, attenuation and phase reversal. A hardware controllable interface is also available. The WM8736 is an ideal device to interface to AC-3, DTS, and MPEG audio decoders for surround sound applications.
FEATURES
* * 6-channel DAC Performance: - 102dB SNR (`A' weighted @ 48kHz), THD+N: -95dB at full scale 5V or 3.3V supply operation Sampling frequency: 8kHz to 96kHz Input data word: 16 to 24-bit Hardware or SPI compatible serial port control modes: - Hardware mode: system clock, reset, mute - Serial control mode: mute, de-emphasis, digital attenuation (256 steps), zero mute, power down
* * * *
APPLICATIONS
* * * * DVD Home theatre systems Digital TV Digital broadcast receivers
BLOCK DIAGRAM
SCKI (2) ML/I2S MC/IWL MD/DM (12) (13) (14) RSTB (10) MODE (8) MUTE (9)
256fs/384fs/512fs
CONTROL INTERFACE
WM8736
SIGMA DELTA MODULATOR (27) OUT0R STEREO DAC (26) GR0 (25) OUT0L
MUTE/ ATTEN BCKIN (3) LRCIN (4) DIN0 (5) DIN1 (6) DIN2 (7) MUTE/ ATTEN SERIAL INTERFACE DIGITAL FILTERS MUTE/ ATTEN
(23) OUT1R SIGMA DELTA MODULATOR STEREO DAC (22) GR1 (21) OUT1L
(19) OUT2R SIGMA DELTA MODULATOR STEREO DAC (18) GR2 (17) OUT2L
(24) (20) AGND2 AGND1
(11) DGND
(16) CAP
(28) (15) AVDD2 AVDD1
(1) DVDD
WOLFSON MICROELECTRONICS LTD
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 Email: sales@wolfson.co.uk www.wolfsonmicro.com
Production Data Datasheets contain final specifications current on publication date. Supply of products conforms to Wolfson Microelectronics' Terms and Conditions.
2001 Wolfson Microelectronics Ltd.
WM8736 PIN CONFIGURATION
DVDD SCKI BCKIN LRCIN DIN0 DIN1 DIN2 MODE MUTE RSTB DGND ML/I2S MC/IWL MD/DM 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AVDD2 OUT0R GR0 OUT0L AGND2 OUT1R GR1 OUT1L AGND1 OUT2R GR2 OUT2L CAP AVDD1
Production Data
ORDERING INFORMATION
DEVICE WM8736EDS TEMP. RANGE -25 to 85 C
o o
PACKAGE 28-pin SSOP
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device.
CONDITION Supply voltage Reference input Operating temperature range, TA Storage temperature Package body temperature (soldering, 10 seconds) Package body temperature (soldering, 2 minutes)
MIN -0.3V -25o C -65o C
MAX +7V VDD + 0.3V +85oC +150oC +240oC +183oC
WOLFSON MICROELECTRONICS LTD
PD Rev 2.1 January 2001
2
Production Data
WM8736
RECOMMENDED OPERATING CONDITIONS
PARAMETER Digital supply range Analogue supply range Ground Difference DGND to AGND Analogue supply current Digital supply current Analogue supply current Digital supply current SYMBOL DVDD AVDD AGND, DGND AVDD = 5V DVDD = 5V AVDD = 3.3V DVDD = 3.3V TEST CONDITIONS MIN -10% -10% -0.3 TYP 3.3 to 5 3.3 to 5 0 0 50 15 45 15 MAX +10% +10% +0.3 UNIT V V V V mA mA mA mA
ELECTRICAL CHARACTERISTICS
Test Conditions AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated. PARAMETER DAC Circuit Specifications SNR (See Notes 1 and 2) SNR with automute on THD (full-scale) (See Note 2) THD+N (Dynamic range) (See Note 2) Frequency response Pass band ripple Transition band Out of band rejection Channel separation Gain mismatch channel-to-channel Digital Logic Levels Input LOW level Input HIGH level Output LOW level Output HIGH level Analogue Output Levels Output level Into 10kohm, full scale 0dB, (5V supply) Into 10kohm, full scale 0dB, (3.3V supply) To midrail or a.c. coupled (5V supply) To midrail or a.c. coupled (3.3V supply) 5V or 3.3V 1.1 0.72 1 1 100 AVDD/2 AVDD to CAP and CAP to AGND 90 AVDD/2 1.8 V
PD Rev 2.1 January 2001
SYMBOL
TEST CONDITIONS AVDD, DVDD = 5V AVDD, DVDD = 3.3V AVDD, DVDD = 5V AVDD, DVDD = 3.3V 0dB -60dB
MIN 95
TYP 102 100 110 108 -96 102
MAX
UNIT dB dB dB dB
-85
dB dB
0 0.125 20,000 -40 90 1
20,000
Hz dB Hz dB dB %FSR
VIL VIH VOL VOH IOL = 2mA IOH = 2mA DVDD - 0.3V 2.0
0.8 GND + 0.3V
V V
VRMS VRMS kohms kohms pF V kohms
Minimum resistance load
Maximum capacitance load Output d.c. level Reference Levels Potential divider resistance Voltage at CAP POR POR threshold WOLFSON MICROELECTRONICS LTD
3
WM8736
Production Data
LRCIN tBCH BCKIN tBCY DIN tDS tDH tBL tBCL tLB
Figure 1 Audio Data Input Timing Test Conditions AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated. PARAMETER BCKIN pulse cycle time BCKIN pulse width high BCKIN pulse width low BCKIN rising edge to LRCIN edge LRCIN rising edge to BCKIN rising edge DIN setup time DIN hold time SYMBOL tBCY tBCH tBCL tBL tLB tDS tDH TEST CONDITIONS MIN 100 50 50 30 30 30 30 TYP MAX UNIT ns ns ns ns ns ns ns Audio Data Input Timing Information
tSCKIL SCKI tSCKIH
Figure 2 System Clock Timing Requirements Test Conditions AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated. PARAMETER System Clock Timing Information SCKI system clock pulse width high SCKI system clock pulse width low tSCKIH tSCKIL 13 13 ns ns SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
WOLFSON MICROELECTRONICS LTD
PD Rev 2.1 January 2001
4
Production Data
WM8736
tMLS tMLL tMLH
ML/12S tMCH MC/IWL tMCY MD/DM tMDS tMDH tMCL
Figure 3 Program Register Input Timing Test Conditions AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated. PARAMETER SYMBOL tMCY tMCL tMCH tMDS tMDH tMLL tMLS tMLH TEST CONDITIONS MIN 100 50 50 30 30 30 30 30 TYP MAX UNIT ns ns ns ns ns ns ns ns Program Register Input Information MC/IWL pulse cycle time MC/IWL pulse width low MD/DM pulse width high MD/DM set-up time MC/IWL hold time ML/I2S pulse width low ML/I2S set-up time ML/I2S hold time Notes: 1. 2. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured "A" weighted over a 20Hz to 20kHz bandwidth. All performance measurements done with 20kHz low pass filter. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values.
WOLFSON MICROELECTRONICS LTD
PD Rev 2.1 January 2001
5
WM8736 PIN DESCRIPTION
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Note: Digital input pins have Schmitt trigger input buffers. NAME DVDD SCKI BCKIN LRCIN DIN0 DIN1 DIN2 MODE MUTE RSTB DGND ML/I2S MC/IWL MD/DM AVDD1 CAP OUT2L GR2 OUT2R AGND1 OUT1L GR1 OUT1R AGND2 OUT0L GR0 OUT0R AVDD2 TYPE Supply Digital input Digital input Digital input Digital input Digital input Digital input Digital input Digital I/O Digital input Supply Digital input Digital input Digital input Supply Analogue output Analogue output Analogue input Analogue output Supply Analogue output Analogue input Analogue output Supply Analogue output Analogue input Analogue output Supply DESCRIPTION Digital positive supply. System clock input (256, 384 or 512fs). Audio data bit clock input. Left sample rate clock input. Channel 0 serial audio data input. Channel 1 serial audio data input. Channel 2 serial audio data input.
Production Data
Mode select pin. Low is software mode, high is hardware control. Internal pull-down. Mute control pin, input or automute output. Low is not mute, high is mute, Z is automute. Reset input - active low. Internal pull-up. Digital ground supply Latch enable (software mode) or input format selection (hardware mode). Internal pull-up. Serial control data clock input (software mode) or input word length selection (hardware mode). Internal pull-up. Serial control data input (software mode) or de-emphasis selection (hardware mode). Analogue positive supply. Analogue internal reference. Left channel 2 output. Channel 2 reference. Right channel 2 output. Analogue ground supply. Left channel 1 output. Channel 1 reference. Right channel 1 output. Analogue ground supply. Left channel 0 output. Channel 0 reference. Right channel 0 output. Analogue positive supply.
WOLFSON MICROELECTRONICS LTD
PD Rev 2.1 January 2001
6
Production Data
WM8736
DEVICE DESCRIPTION
WM8736 is a complete 6-channel stereo audio digital-to-analogue converter, including digital interpolation filter, multi-bit sigma delta with dither, and switched capacitor multi-bit stereo DAC and output smoothing filters. The device is implemented as three separate stereo DACs in a single package and controlled by a single interface. Three separate data input pins are provided for each of the three separate stereo DACs, and LRCIN, BCKIN and SCKI are shared between them. Control of internal functionality of the device is by either hardware control (pin programmed) or software control (serial interface). The MODE pin selects between hardware and software control. In software control mode, an SPI type interface is used. This interface may be asynchronous to the audio data interface. Control data will be re-synchronized to the audio processing internally. Operation using system clock of 256fs, 384fs or 512fs is provided, selection between clock rates being automatically controlled in hardware mode, or serial controlled when in software mode. Sample rates (fs) from less than 8ks/s to 96ks/s are allowed, provided the appropriate system clock is input. The data interface supports normal (Japanese right justified) and I2S (Philips left justified, one bit delayed) interface formats, in both `packed' and unpacked forms. When in hardware mode, the three serial interface pins become control pins to allow selection of input data format type (I2S or normal), input word length (16, 18, 20, or 24-bit) and de-emphasis function.
SYSTEM CLOCK
The system clock for WM8736 must be either 256fs, 384fs or 512fs, where fs is the audio sampling frequency (LRCIN) typically 32kHz, 44.1kHz, 48 or 96kHz. The system clock is used to operate the digital filters and the noise shaping circuits. WM8736 has a system clock detection circuit that automatically determines what the system clock frequency relative to the sampling rate is (to within +/- 8 system clocks). If greater than 8 clocks error, then the interface shuts down the DAC and mutes the output. The system clock should be synchronised with LRCIN, but WM8736 is tolerant of phase differences or jitter on this clock. Severe distortion in the phase difference between LRCIN and the system clock will be detected, and cause the device to automatically resynchronise. If the externally applied LRCIN slips in phase by more than half the internal LRCIN period, which is derived from master clock, then the interface resynchronises. Such a case would, for example, occur if repeated LRCIN clocks were received with only 252 systems clocks per period. In this case the interface would only resynchronise once every 64 LRCIN periods, even if jitter was present on the LRCIN signal. During resynchronisation, the device will either repeat the previous sample, or drop the next sample, depending on the nature of the phase slip. This will ensure no discernible "click" at the analogue outputs during resynchronisation. Table 1 shows the typical system clock frequency inputs for the WM8736. SAMPLING RATE (LRCIN) SYSTEM CLOCK FREQUENCY (MHZ) 384fs 512fs 16.384 22.5792 24.576
256fs
32kHz 8.192 12.288 44.1kHz 11.2896 16.9340 48kHz 12.288 18.432 96kHz 24.576 36.864 Table 1 System Clock Frequencies Versus Sampling Rate
AUDIO DATA INTERFACE
The Serial Data interface to WM8736 is fully compatible with both normal (MSB first, right-justified) or I2S interfaces. Data may be `packed' (number of serial bit clocks per LRCIN period is exactly 2 times the number of data bits, i.e. normally 32 in 16-bit mode) or unpacked (more than 32 bit clocks per LRCIN period). The WM8736 will automatically detect 16-bit packed data being sent to the device in normal mode, and accept the data in this input format accordingly.
WOLFSON MICROELECTRONICS LTD
PD Rev 2.1 January 2001
7
WM8736
I2S MODE 0 1 Table 2 Serial Interface Formats
1/fs
Production Data DESCRIPTION Normal format (MSB-first, right Justified) I2S format (Philips serial data protocol )
LEFT CHANNEL LRCIN
RIGHT CHANNEL
BCKIN
DIN
1 MSB
2
3
n-2 n-1 n LSB
1
2
3
n-2 n-1 n LSB
MSB
Figure 4 `Normal' Data Input Timing
1/fs
LEFT CHANNEL LRCIN
RIGHT CHANNEL
BCKIN
DIN
1 MSB
2
3
n-2 n-1 n LSB
1
2
3
n-2 n-1 n LSB
MSB
Figure 5 I2S Data Input Timing
WOLFSON MICROELECTRONICS LTD
PD Rev 2.1 January 2001
8
Production Data
WM8736
MODES OF OPERATION
Control of the various modes of operation is either by software control over the serial interface, or by hard-wired pin control. Selection of software or hardware mode is via MODE pin. The following functions may be controlled either via the serial control interface or by hard wiring of the appropriate pins. FUNCTION OPTIONS Input audio data format Normal format I2S format 16 18 20 24 On Off On Off WM8736 off WM8736 on Lch/Rch = High/Low Lch/Rch = Low/High Lch, Rch individually Lch, Rch common On Off Enabled Disabled See Table 7 for all options SOFTWARE CONTROL DEFAULT VALUE PIN 8: MODE = 0 I2S = 0 (default) I2S = 1 IW[1:0] = 00 (default) IW[1:0] = 11 IW[1:0] = 01 IW[1:0] = 10 DE = 1 DE = 0 (Default) MU = 1 MU = 0 (default) Available from Pin 10: RSTB LRP = 0 (default) LRP = 1 ATC = 0; 0dB (default) ATC = 1 IZD = 1 IZD = 0 (default) OPE = 0 (default) OPE = 1 Default is PL[3:0] = 1001, stereo mode Automute function controlled from MUTE pin low = not mute Z = automute enable high = muted Not available in hardware mode Not available in hardware mode, default 0dB HARDWARE CONTROL BEHAVIOUR PIN 8: MODE = 1 Pin 12, 13: ML/I2S, MC/IWL = 00 or 01 or 10 Pin 12, 13: ML/I2S, MC/IWL = 11 Pin 12, 13: ML/I2S, MC/IWL = 00 Pin 12, 13: ML/I2S, MC/IWL = 11 (I2S only) Pin 12, 13: ML/I2S, MC/IWL = 01 Pin 12, 13: ML/I2S, MC/IWL = 10 Pin 14: MD/DM = 1 Pin 14: MD/DM = 0 Pin 9: MUTE = 1 Pin 9: MUTE = 0 Pin 10: RSTB = 0 Pin 10: RSTB = 1 Not available in hardware mode, default value set
Input word length
De-emphasis selection
Mute
Reset and power down control Input LRCIN polarity
Volume control
Infinite zero detect Operation enable (OPE) DAC output control
Table 3 Control Function Summary
WOLFSON MICROELECTRONICS LTD
PD Rev 2.1 January 2001
9
WM8736
HARDWARE CONTROL MODES
Production Data
When the MODE pin is held high the following hardware modes of operation are available.
MUTE AND AUTOMUTE OPERATION
In both hardware and software modes pin 9 (MUTE) controls selection of MUTE directly, and can be used to enable and disable the automute function, or as an output of the automuted signal.
IZD (Register Bit) AUTOMUTED (Internal Signal) 10k MUTE PIN SOFTMUTE (Internal Signal)
MU (Register Bit)
Figure 6 Mute Circuit Operation The MUTE pin behaves as a bi-directional function, that is, as an input to select MUTE or NOTMUTE, or as an output indication of automute operation. MUTE is active high; taking the pin high causes the filters to soft mute, ramping down the audio signal over a few milliseconds. Taking MUTE low again allows data into the filter. The automute function detects a series of zero value audio samples of 1024 samples long being applied to both left and right channels. After such an event, a latch is set whose output (AUTOMUTED) is wire OR'ed through a 10kohm resistor to the MUTE pin. Thus if the MUTE pin is not being driven, the automute function will assert MUTE. If MUTE is tied low, AUTOMUTED is overidden and will not mute. If MUTE is driven from a source follower, or diode, then both MUTE and automute functions are available. If MUTE is not driven, AUTOMUTED appears as a weak output (10k source impedance) so can be used to drive external mute circuits. The automute signal is AND'ed with IZD, this qualified mute signal then being OR'ed into the SOFTMUTE control. Therefore, in software mode, automute operation may be controlled with IZD control bit.
I S INPUT FORMAT SELECTION AND MC/IWL INPUT FORMAT SELECTION
In hardware mode, pins 12 and 13 become input controls for selection of input data format type and input data word length, see Table 4. I2S mode is designed to support any word length provided enough bit clocks are sent. I2S 0 0 1 1 MC/IWL 0 1 0 1 INPUT DATA MODE 16-bit normal 20-bit normal 24-bit normal I2S mode
2
Table 4 Control of Input Data Format Type and Input Data Word Length
MD/DM DE-EMPHASIS
In hardware mode, pin 14 becomes an input control for selection of de-emphasis filtering to be applied. see Table 5. MD/DM MD/DM Table 5 De-emphasis Control 0 1 De-emphasis off De-emphasis on
WOLFSON MICROELECTRONICS LTD
PD Rev 2.1 January 2001
10
Production Data
WM8736
RSTB RESET AND POWER DOWN CONTROL
In both hardware and software modes, this pin resets the entire device when taken low. The device remains powered down while RSTB is held low. RSTB RSTB 0 1 Device powered down and reset Device powered up and active
Table 6 Reset and Power Down Control
SOFTWARE CONTROL INTERFACE
The WM8736 can be controlled using a 3-wire serial interface. MD/DM (pin 6) is used for the program data, MC/IWL (pin 5) is used to clock in the program data and ML/I2S (pin 4) is use to latch in the program data. The 3-wire interface protocol is shown in Figure 7.
ML/I2S
MC/IWL
MD/DM
B2
B1
B0
A3
A2
A1
A0
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 7 3-Wire Serial Interface
REGISTER MAP
WM8736 controls the special functions using 9 program registers, which are 16-bits long. These registers are all loaded through input pin MD/DM. After the 16 data bits are clocked in, ML/I2S is used to latch in the data to the appropriate register. Table 7 shows the complete mapping of the 9 registers. B2 M0 M1 M2 M3 M4 M5 M6 M7 M8 B1 B0 NOT USED A3 0 0 0 0 0 0 0 0 1 A2 A1 ADDRESS 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 A0 0 1 0 1 0 1 0 1 0 D8 LDL LDR PL3 IZD LDL LDR LDL LDR LDM D7 AL7 AR7 PL2 AL7 AR7 AL7 AR7 AM7 D6 AL6 AR6 PL1 AL6 AR6 AL6 AR6 AM6 D5 AL5 AR5 PL0 AL5 AR5 AL5 AR5 AM5 D4 DATA AL4 AR4 IW1 AL4 AR4 AL4 AR4 AM4 D3 AL3 AR3 IW0 AL3 AR3 AL3 AR3 AM3 D2 AL2 AR2 OPE ATC AL2 AR2 AL2 AR2 AM2 D1 AL1 AR1 DE LRP AL1 AR1 AL1 AR1 AM1 D0 AL0 AR0 MU I2S AL0 AR0 AL0 AR0 AM0
Table 7 Mapping of Program Registers
WOLFSON MICROELECTRONICS LTD
PD Rev 2.1 January 2001
11
WM8736
REGISTER NAME Register M0 A[3:0] = 0000 Register M1 A[3:0] = 0001 Register M2 A[3:0] = 0010 BIT NAME AL[7:0] LDL AR[7:0] LDR MU DE OPE IW[1:0] PL[3:0] I2S LRP ATC SF[1:0] IZD AL[7:0] LDL AR[7:0] LDR AL[7:0] LDL AR[7:0] LDR AM[7:0] LDM DEFAULT 1111 1111 0 1111 1111 0 0 0 0 00 1001 0 0 0 00 0 1111 1111 0 1111 1111 0 1111 1111 0 1111 1111 0 1111 1111 0 DESCRIPTION
Production Data
Register M3 A[3:0] = 0011
Register M4 A[3:0] = 0100 Register M5 A[3:0] = 0101 Register M6 A[3:0] = 0110 Register M7 A[3:0] = 0111 Register M8 Master Gain A[3:0] = 1000
Attenuation data for left channel DAC 0 Attenuation data load control for left channel DAC 0 Attenuation data for right channel DAC 0 Attenuation data load control for right channel DAC 0 Left and right DACs soft mute control De-emphasis control Left and right DACs operation control Input audio word resolution DAC output control Audio data format select Polarity of LRCIN (pin 4) Select Attenuator control Sampling rate select Infinite zero detection circuit control and automute control Attenuation data for left channel DAC 1 Attenuation data load control for left channel DAC 1 Attenuation data for right channel DAC 1 Attenuation data load control for right channel DAC 1 Attenuation data for left channel DAC 2 Attenuation data load control for left channel DAC 2 Attenuation data for right channel DAC 2 Attenuation data load control for right channel DAC 2 DAC attenuation data for all channels Attenuation data load control for all channels
Table 8 Internal Register Mapping
DAC OUTPUT ATTENUATION
Registers M0 and M1 control the left and right channel attenuation of DAC 0. Registers M4 and M5 control the left and right channel attenuation of DAC 1. Registers M6 and M7 control the left and right channel attenuation of DAC 2. Register M8 is a master register that can be used to control attenuation of all channels. Register M0 (A[3:0] = 0000) is used to control left channel 0 attenuation. Bits 0-7 (AL[7:0]) are used to determine the attenuation level (Table 9). The level of attenuation is given by: Attenuation = [20.log10 (Attenuation_Data/256)] dB AX[7:0] 00(hex) 01(hex) : : : FE(hex) FF(hex) ATTENUATION LEVEL -dB (mute) -48.16dB : : : -0.07dB 0dB Eqn. 1
Table 9 Attenuation Control Levels Bit 8 in register M0 (LDL) is used to control the loading of attenuation data in AL[7:0]. When LDL is set to 0, attenuation data will be loaded into AL[7:0], but it will not affect the attenuation level until LDL is set to 1. Register M1 (A[1:0] = 01) is used to control right channel attenuation in the same manner. Attenuation of DAC 1 and 2 are similarly controlled. Bit 2 in register M3 (A[3:0] = 0011) is used to control the attenuator (ATC). When ATC is high, the attenuation data loaded in the left channel program register is used for both the left and the right channels. Therefore, DAC 0 attenuation data for left and right channels is read from register M0, DAC 1 attenuation data for left and right channels is read from register M4 and DAC 2 attenuation data for left and right channels is read from register M6. When ATC is low, attenuation data is read from the individual left and right DAC registers. WOLFSON MICROELECTRONICS LTD
PD Rev 2.1 January 2001
12
Production Data
WM8736
The master gain register M8 (A[3:0] = 0110) is used to write a gain value to all channels simultaneously. Bit 8 (LDM) controls the update in the same way as the attenuation registers, and is to be set to 1 for correct operation in this mode.
LEFT AND RIGHT DAC SOFT MUTE CONTROL
Soft mute is controlled by setting bit MU, register M2:bit 0. A high level on MU (MU = 1) will cause the output to be muted, the effect of which is to ramp the signal down in the digital domain so that there is no discernible click. This can be seen in Figure 6 Mute Circuit Operation.
DE-EMPHASIS CONTROL
Bit 1 (DE) in register M2 is used to control digital de-emphasis. A low level on bit 1 (DE = 0) disables de-emphasis whilst a high level enables de-emphasis (DE = 1). De-emphasis applied to the filters shapes the frequency response of the digital filter according to the input sample frequency.
LEFT AND RIGHT DAC OPERATION CONTROL
Bit 2 (OPE) in register M2 is used for operation control. With OPE = 0 (default) the device functions normally. With OPE = 1 the device is disabled and the outputs are held at midrail. Current consumption of the digital section is minimized, but analogue sections remain active in order to preserve d.c. levels.
INPUT AUDIO WORD RESOLUTION
WM8736 allows maximum flexibility over the control of the audio data interface, allowing selection of format type, word length, and sample rates. Bits 3 and 4 of register M2 (IW[1:0]) are used to determine the input word resolution. WM8736 supports 16-bit, 18-bit, 20-bit and 24-bit formats as described in Table 10. BIT 4 (IW1) 0 0 1 1 Table 10 Input Data Resolution BIT 3 (IW0) 0 1 0 1 INPUT RESOLUTION 16-bit data word 20-bit data word 24-bit data word 18-bit data word
DAC OUTPUT CONTROL
Bits 5, 6, 7 and 8 (PL[3:0]) of register M2 are used to control the output format as shown in Table 11. PL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 PL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 PL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 PL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 LEFT OUTPUT MUTE L R (L + R)/2 MUTE L R (L + R)/2 MUTE L R (L + R)/2 MUTE L R (L + R)/2 RIGHT OUTPUT MUTE MUTE MUTE MUTE L L L L R R R R (L + R)/2 (L + R)/2 (L + R)/2 (L + R)/2 NOTE Mute both channels
Reverse channels
Stereo mode
Mono mode
Table 11 Programmable Output Format
WOLFSON MICROELECTRONICS LTD
PD Rev 2.1 January 2001
13
WM8736
SERIAL PROTOCOL
Production Data
Bits 0 (I2S) and 1 (LRP) of register M3 are used to control the input data format completely. A low on bit 0 (I2S = 0) sets the format to Normal (MSB-first, right justified Japanese format), whilst a high (I2S = 1) sets the format to I2S (Philips serial data protocol).
POLARITY OF LRCIN SELECT
Bit 1 (LRP) of register M3 is used to control the polarity of LRCIN (sample rate clock). When bit 1 is low (LRP = 0), left channel data is assumed when LRCIN is in a high phase and right channel data is assumed when LRCIN is in a low phase. When bit 1 is high (LRP = 1), the polarity assumption is reversed.
INTERFACE CLOCKS AND SAMPLING RATES
Bits 6 (SF0) and 7 (SF1) of register M3 are used to control the sampling frequency, as shown in Table 12. SF0 0 0 1 1 SF1 0 1 0 1 SAMPLING FREQUENCY 44.1kHz group 48kHz group 32kHz group Reserved 22.05 / 44.1 / 88.2kHz 24 / 48 / 96kHz 16 / 32 / 64kHz Not defined
Table 12 Sampling Frequencies
INFINITE ZERO DETECTION
Bit 8 (IZD) in register M3 controls operation of the automute function. If IZD (Infinite Zero Detect) is high, 1024 consecutive zero audio samples will force the ouput to zero. See Figure 6. Note that the control of pin MUTE also affects automute operation. To turn off automute, pin MUTE must be held low as well as IZD being low (default).
WOLFSON MICROELECTRONICS LTD
PD Rev 2.1 January 2001
14
Production Data
WM8736
RECOMMENDED EXTERNAL COMPONENTS
DVDD 1 + C1 C2 11 DGND DVSS AVSS1 AVSS2 12 20 24 DVDD AVDD1 AVDD2 15 28
AVDD
+ C3 C4 C5
AGND 26 22 18 C6
ML/I2S MC/IWL MD/DM0 RSTB
GR0 GR1 GR2
Software I/F or Hardware Control
13 14 10
OUT0R 8 MODE
27
WM8736
OUT0L 25 23
C7
AC-Coupled OUT0R/L to External LPF AC-Coupled OUT1R/L to External LPF AC-Coupled OUT2R/L to External LPF
+ +
9
MUTE OUT1R
C1
+
2 3 4
SCKI BCKIN LRCIN DIN0 DIN1 DIN2 OUT2L 17 OUT2R 19 OUT1L 21
C9
Audio Serial Data I/F
5 6 7
C10
C11
+ + +
16 + C12 C13
CAP
NOTES:
1. AGND and DGND should be connected as close to the WM8736 as possible. 2. C2, C3, C4 and C 12 should be positioned as close to the WM8736 as possible. 3. Capacitor types should be carefully chosen. Capacitors with very low ESR are recommended for optimum performance. AGND
Figure 8 External Components Diagram
RECOMMENDED EXTERNAL COMPONENTS VALUES
COMPONENT REFERENCE C1 and C5 C2 to C4 C6 to C11 C12 C13 SUGGESTED VALUE 10F 0.1F 10F 0.1F 10F DESCRIPTION De-coupling for DVDD and AVDD. De-coupling for DVDD and AVDD. Output AC coupling caps to remove midrail DC level from outputs. Reference de-coupling capacitors for CAP pin.
Table 13 External Components Description
WOLFSON MICROELECTRONICS LTD
PD Rev 2.1 January 2001
15
WM8736 APPLICATIONS RECOMMENDED
SURROUND SOUND DECODER BCK LRCK
(FRONT)
Production Data
WM8736
DAC
FRONT
DATA
(SURROUND) DATA (CENTRES/SUBWOOFER) DATA
256fs OR 384fs
DAC
SURROUND
CENTRE 3 MCU DAC SUBWOOFER
WOLFSON MICROELECTRONICS LTD
PD Rev 2.1 January 2001
16
Production Data
WM8736
PACKAGE DIMENSIONS
DS: 28 PIN SSOP (10.2 x 5.3 x 1.75 mm) DM007.C
b
28
e
15
E1
E
1
D
14
GAUGE PLANE
0.25 c A A2 A1 L
-C0.10 C
SEATING PLANE
Symbols A A1 A2 b c D e E E1 L REF: MIN ----0.05 1.62 0.22 0.09 9.90 7.40 5.00 0.55 o 0
Dimensions (mm) NOM --------1.75 --------10.20 0.65 BSC 7.80 5.30 0.75 o 4 JEDEC.95, MO-150
MAX 2.0 ----1.85 0.38 0.25 10.50 8.20 5.60 0.95 o 8
NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM. D. MEETS JEDEC.95 MO-150, VARIATION = AH. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
WOLFSON MICROELECTRONICS LTD
PD Rev 2.1 January 2001
17

▲Up To Search▲

Price & Availability of WM8736

	To Download WM8736 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .